The present invention generally relates to the control and attenuation of electrostatic discharge (ESD) to prevent damage to integrated circuits (IC). The invention enables isolation of ICs from voltage drops caused by ESD current. More specifically, the invention implements a divided rail concept to strategically direct undesirable ESD current away from sensitive circuitry.
Integrated circuits (ICs) normally require a special electrostatic discharge (ESD) protection circuit for all pads. ESD is a discharge of static electricity that can destroy sensitive electronic devices and circuitry unless major steps are taken to prevent its occurrence. ESDs are generally stored on non-conductive surfaces and dielectric components of IC devices. Both discreet semi-conductor devices and integrated circuits may be damaged by ESD. Specifically, as ICs have achieved a higher speed, smaller geometries, lower power and lower voltage, they have become more susceptible to ESD damage.
Prior art ESD protection circuit systems include special low impedance elements such as, for example, forward biased diodes or snap back devices that route the ESD current to one of two power supply rails, depending upon the polarity of the ESD pulse. In these systems, typically, the ESD current is directed through a power supply rail to complete the ESD discharge circuits. For normal operation of an IC, the voltage, at any point along a metal rail, is the same as any other point within a difference of a few millivolts. However, during an ESD episode, the interconnect conducts a large ESD current. This may include sizeable and potentially destructive voltage drops along the interconnect because of the large ESD current flowing through the resistance of the metal rail.
Regarding the prior art, ESD protection circuits operate under a high voltage potential and would cause irreversible damage if used in small potential circuits. For example, U.S. Pat. No. 4,692,834 to Iwashi et al, discloses an electrostatic discharge protection circuit with variable limiting thresholds for MOS device. Specifically, the invention relates to the protection from over voltage damage, a MOS input device which is to be responsive to a high voltage input signal. The invention implements a variable limiting threshold for an input signal as part of the electrostatic discharge protection circuit. Specifically, the invention utilizes a gate controlled diode utilizing a gate controlled drain avalanche breakdown. In this embodiment, a preselected potential is continuously or optionally applied to the gates of the gate controlled diode from the exterior or interior of the integrated circuit, so that the potential limiting threshold for the input signal is enhanced. Thereafter, a high voltage input signal for the MOS input semiconductor integrated circuit is free from potential limiting operation and the integrated circuit can receive the information of the high voltage input signal.
Further, U.S. Pat. No. 5,237,395 to Lee, discloses a power rail ESD protection circuit. Specifically, first and second current shunt passes between the power rails are maintained non-conductive during normal circuit operation, and are triggered to a conductive mode in response to an ESD event on the power rail. A triggering circuit may employ a logic gate such as an inverter, with its input coupled to the positive power rail that maintains a low level output during normal operation and provides a high output in response to an ESD event on the power rail.
U.S. Pat. No. 5,287,241 to Puar, discloses a shunt circuit for electrostatic discharge protection. Specifically, the invention discloses a circuit that is added to a complementary metal oxide silicone (CMOS) integrated circuit (IC) to provide an intentional non-reversed biased Vdd to Vss shunt pass for transient currents such as electrostatic discharges. The circuit protects the IC from ESD damage by turning on before any other pass, thus directing the ESD transient current away from easily damaged structures. More specifically, the ESD transient current is steered from the VVD rail to the Vss rail through the on conduction of a P-channel transistor whose source and drain are connected to Vdd and Vss respectively. The voltage on the gate of this transistor follows the Vdd supply rail because it is driven by a delay network formed by a second transistor in a capacitor. This Vdd tracking delay network turns the Vdd to Vss transistor on during a transient and off during normal operation of the IC.
U.S. Pat. No. 5,473,500 to Payne et al, relates to electrostatic discharge circuits for high speed, high voltage circuitry. Specifically, the invention relates to a protection circuit which includes a first controlled path for discharging negative ESD pulses introduced at the signal node. The first controlled path is from the signal node to Vcc via the source and drain electrodes of a first transistor. The gate of the transistor is at a soft ground by connection of the gate through a resistor and an inverter to a fixed voltage supply potential (Vcc). A second controlled path discharges positive ESD pulses via source and drain regions of serially connected second and third transistors to ground. The second transistor has a ate tied at Vcc by means of a resistor and inverter to ground. The third transistor is at soft ground by means of a resistor and inverter to Vcc. The third transistor is turned on by a positive voltage exceeding the threshold voltage of the third transistor. The protection circuit may include a third controlled path through a fourth transistor, if low voltage circuitry is tied to the signal node. The fourth transistor includes a gate that is tied high by connection of the gate to ground via transistor and inverter.
U.S. Pat. No. 5,530,612 to Maloney, relates to electrostatic discharge protection circuits using biased and terminated PNP transistor chains. Specifically, the disclosure relates to a bias network that is used to augment the diode string to distribute small but significant forward current to the diodes. Also disclosed is the use of cantilever diodes which provide PNP Darlington gain block for ESD protection rather than for amplifying signals in bipolar ICs. In one disclosure, the termination is the principal element of device novelty and that which makes the protection device xe2x80x9cstand-alonexe2x80x9d. The termination supplies final base current to the gain block for a limited amount of time, so that ESD charge can be shunted harmlessly through the PNP chain, but assures that the structure draws no current from a stable power supply long term. The entire structure is able to absorb noise spikes as well as ESD pulses. The termination also makes provisions for discharging its capacitor between ESD pulses, as is necessary for standardized testing. The invention is specifically suited for an IC power supply clamp, and reduces the damage often seen on IC C power supplies during extensive ESD testing.
U.S. Pat. No. 5,584,870 to Single et al, describes an implant ESD protection network. Specifically, the invention relates to a protective component that is provided for protecting a cochlear implant from external electrostatic discharges. The implant receives signals through a receiver coil inductively coupled to a transmitter coil. The protective component is disposed across the coil of the transmitter.
U.S. Pat. No. 5,644,460 to Clukey, discloses a multi-rail electrostatic discharge protection device. The invention relates to a device for protecting against circuit damaging voltage spikes at input nodes and output nodes of electrical circuits and between high and low potential power rails. The voltage spikes are of the type identified generally as electrostatic discharges. The device includes a plurality of semiconductor elements which are preferably bipolar transistors, coupled to the power rails and an input node or an output node of the circuit such that all types of electrostatic discharges can be diverted using the single device of the present invention. In a preferred embodiment, the transistors have a common collector, their bases are open, and they are configured so that the emitter of one transistor is coupled to a high potential power rail. The emitter of a second transistor is coupled to a low potential rail, and the emitter of a third transistor is coupled to the node to be protected. Various combinations of the breakdown characteristics of the several coupled transistors operate to divert various types of voltage spikes, including positive and negative spikes at the node, and positive and negative spikes between the power rails.
U.S. Pat. No. 5,610,790 to Staab et al, discloses a method and structure for providing ESD protection for silicone on insulator integrated circuits. The ESD protection circuit includes an electrically conductive pad and first conductor segment fabricated over an insulating layer. The first conductor segment connects the pad directly to a first node, without an intervening input resistor. A first diode is fabricated over an insulating layer and connected between the first node and a first voltage supply rail. Similarly, a second diode is fabricated over the insulating layer and connected between the first node and a second voltage supply rail. Ballast resistors can be included in series with each of the diodes. A cross power supply clamp, also fabricated over the insulating layer, is connected between the first and second voltage supply rails. The first node of the ESD protection circuit is coupled to the SOI integrated circuit to be protected. The ESD protection circuit can be fabricated on a minimum number of silicon islands to improve local thermal spreading. Improved ESD protection is provided to input, output and I/O pins of an SOI integrated circuit, while promoting high speed signal transfer between these pins and the integrated circuit.
U.S. Pat. No. 5,610,791 to Voldman, discloses a power sequence independent electrostatic discharge protection circuits. The invention provides ESD protection in an IC chip having multiple power supply rails. The ESD protection circuitry protects each power supply rail from an ESD impulse with respect to ground and with respect to the other power supply rails. The ESD protection circuitry is power sequence independent thereby eliminating any restrictions on the sequencing of power as applied to, and removed from, the different power supply rails of the IC chip. A discharge device is controlled by a biasing device such that ESD impulses are passed through the discharge device, but power supply current is not passed therethrough during power sequencing.
U.S. Pat. No. 5,617,283 to Krakauer et al, discloses a self-referencing modulation circuit for CMSOS integrated circuit electrostatic discharge protection clamps. The modulation circuit in this invention includes a diode stack coupled to a resistor and further coupled to an inverter powered by the signal pad voltage in one embodiment, or an odd plurality of series connected inverters powered by the signal pad voltage in al alternate embodiment. The inverter chain is coupled to the esd clamp. The modulation circuit requires no reference supply voltage to operate. The ESD protection circuit shunts currents associated with ESD events away from the ICs as well as clamping I/O pad voltages to acceptable levels during an ESD event.
U.S. Pat. No. 5,637,892 to Leach, discloses an electrostatic discharge protection in integrated circuits, systems and methods. The system includes a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit.
U.S. Pat. No. 5,654,574 to Williams et al, discloses an electrostatic discharge protection device for integrated circuits. The system includes a pair of depletion mode MOSFETTs connected drain-to-drain in a series path between an input terminal and an output terminal, the gate of each MOSFET being connected to its source. A first diode having a relatively high breakdown voltage is connected between ground and the common drain terminal of the MOSFETs and a second diode having a relatively low breakdown voltage is connected between ground and the output terminal of the device. The second diode breaks down during a relatively low, long-lived voltage spike while the second MOSFET saturates, liming the size of the current through the second diode. The first diode breaks down during a large voltage spike of short duration, such as occurs from an ESD.
U.S. Pat. No. 5,945,713 to Voldman, discloses electrostatic discharge protection circuits for mixed voltage interface and multi-rail applications. Generally, the invention includes a circuit comprising a first well biased through an EFET so that the ESD circuit is not forward by normal operation when the voltage on the pad rises above a rail voltage.
U.S. Pat. No. 5,946,176 to Ghoshal, discloses an electrostatic discharge protection utilizing microelectromechanical switch. The invention provides a circuit formed within a semiconductor substrate. The circuit has an input and a ground. A voltage activated microelectromechanical switch is fabricated within the semiconducting substrate utilizing integrated circuit techniques. The microelectromechanical switch is coupled across the circuit input and the circuit ground. The voltage activated microelectromechanical switch couples the circuit input to the circuit ground when an electrostatic discharge voltage of sufficient magnitude is applied to the input of the circuit such that electrostatic discharge is dissipated to ground through the microelectromechanical switch thereby protecting the circuit from ESD.
Accordingly, there is a need to route most of the large ESD current away from sensitive core and through the ESD interconnects. Since the core rails conduct only a small fraction of the total ESD current, the voltage drops associated with the core circuitry is reduced to a small, harmless level.
The present invention relates to ESD protection systems incorporated in a circuit. The system, preferably, implements a divided rail scheme in which large ESD currents are directed away from sensitive circuitry. Specifically, the invention provides a divided rail structure and associated diodes, clamps and resistors that manage the routing of destructive ESD currents through the ESD interconnects.
As is well known in the art, the voltage (potential) at any point along a rail is constant. However, when an ESD is encountered, the interconnects develop substantial voltage drops due to current flowing through the rail resistance. This voltage drop presents a serious hazard to sensitive circuits. The present invention implements the divided rail scheme to segregate the voltage drop to be confined in a rail structure adopted to absorb and attenuate the high voltage ESD. Specifically, the divided rail scheme of the present invention, inter alia, includes the bifurcation of the Vdd and Vss rails. As used herein, the term xe2x80x9crailxe2x80x9d refers to a wide variety of metal interconnect that conduct current from bonding pads to the circuitry.
In an exemplary embodiment, the divided rail scheme of the present invention provides a structure in which the Vdd rail is divided into Vdd-esd and Vdd-core. Similarly, Vss rail is divided into Vss-esd and Vss-core. The Vdd-esd and Vss-esd rails and associated circuitry are designed to absorb ESD discharge and hand-off modified, ESD-disabled current to Vdd-core and Vss-core thus protecting sensitive circuitry.